Event Monitor/Recorder Counters register. Allows reading the counters associated with the event channels.
COUNTER0 | Value of the counter for event 0. If the counter reaches full count (the value 7), it remains there if additional events occur. This counter is cleared when the corresponding EVx bit in the ERSTATUS register is cleared by software. |
RESERVED | Reserved. The value read from a reserved bit is not defined. |
COUNTER1 | Value of the counter for event 1. See description for COUNTER0. |
RESERVED | Reserved. The value read from a reserved bit is not defined. |
COUNTER2 | Value of the counter for event 2. See description for COUNTER0. |
RESERVED | Reserved. The value read from a reserved bit is not defined. |